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SIP Solution
 

 

SIP Solution

EES had successfully developed the SIP (MCM) solutions for our customers achieving the high device performance, smaller package size and lower cost. There are several solutions be used by difference package types, which include the BGA, QFP and WCSP with Side by side, Stack
Dies solutions.

Product Package Type Body Size KGD
DTV TFBGA196 12*12 ASIC, AFE, SDRAM
Security Camera TFBGA169 11*11 ASIC, Flash, SDRAM, Conroller
Metrology QFP216 24*24 ASIC

 

Success Case 1:

  1. Application: DTV
  2. Package Type: LFBGA 208, 12mm*12 ^mm
  3. Die Structure: 3 Dies Package ( Stack Dies + Side by Side)
  4. Die Information: EES002 + eFlash + AFE

 

 

 

 
     
   

 

Success Case 2:

  1. Application: Security Camera
  2. Package Type: LFBGA 169, 11mm*11 ^mm
  3. Die Structure: 4 Dies Package (Stack Dies + Side by Side)
  4. Die Information: EES002 + eFlash + SDRAM + Controller

 

 

 

 
     
 
 

 

Step 1: Provide Chip Information
Provide PPA file (define: Internal /External Connection)
Critical Electric Requirement
Step 2: Contract Sign
Step 3:

Starting Substrate Design ( 2 ~ 4 weeks)
Final Spec. Confirm, Substrate Design Sign Back
Starting Substrate Process ( 5~ 8 weeks)
Step 4: Engineering Run
Step 5: Delivery