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Yield & Failure Analysis

Primary responsibility of our Product Engineering group is to maximize yield from each wafer. EE Solutions monitor yields and work closely with both the foundry engineers and assembly house to maximize the yield in order to get the best possible cost to our customers.

EE Solutions offers a full range of quality services for the entire product life cycle. Yield optimization services include yield analysis, corner lot characterization and process re-targeting. We assist customers during the validation and debugging phase by providing benchmark measurements. EE Solutions provides die and packaging qualification including burn-in, ESD, latch up and high accelerated stress test.

We provide complete support to new products including new product qualification, sophisticated failure analysis and optimization.

The skill of yield improvement

9

 

Design Window vs. Process Margin Check

3

 

Product Reliablity Qualification

  1. Reliability Qualification Requested by Customers

  2. Qualification Plan, Sampling Size, Items
    - Base on Customer Plan
    - Ref. on the Industrial Standard
    - Reference From Assembly House

  3. Provide the Reliability Report
    - Date Analysis and Suggestion
  4. Provide the Failure Analysis & Corrective Action


Total Solutions on Reliability Test

Test Item Test Condition Readout (Hour or Cycle) Test Method
Operating Life Test (OLT) Ta = 125¢J, .3*Vcc
Rated current
I = 30 mA
VR = 32V
168/500/1000 (HR) MIL-STD-750C
MIL-STD-883D
METHOD 1005.7
CONDITION  D
METHOD 1027.1
Pressure Cooker Test (PCT)  Ta = 121¢J
P = 15psig, (2ATM)
RH = 100%
48/96/168 (HR) MIL-STD-19500E 
Moisture Resistance Ta = 85¢J
RH = 85%
168/500/1000 (HR) MIL-STD-750C
MIL-STD-883D
Temperature Humidity test (THT) Ta = 85¢J
RH = 85%
168/500/1000 (HR) JEDEC22-A101-B
Temperature Humidity with Bias Test (THBT) Ta = 85¢J
RH = 85%
Bias¡G0~60V
Current¡G¡Ø6A
168/500/1000 (HR) JEDEC22-A101-B
Thermal Shock  Test (TST) -55¢J/5mins to 150¢J/5mins 100 CYC MIL-STD-750C
MIL-STD-883D
Temperature Cycling Test (TCT)  -55¢J/15mins to 125¢J/15mins,
Dwell time¡G1~5mins
500/1000 CYC MIL-STD-750C
MIL-STD-883D
METHOD 1051.2 CONDITION C
JESD22-A104-B
High Temperature Storage Life Ta = 150¢J 168/500/1000 (HR) MIL-STD-750C
JESD22-A103-B

 

Total Solutions on ESD, Latch-up Test

Test Item
Test Condition
Readout (Hour or Cycle)
Test Method
Electrostatic Discharge (ESD) Ta = 25¢J, RH < 55%,
Vdd & Vss to all pins
HBM ¡Ö 2KV
MM ¡Ö 200V
VSS (¡Ó)
VCC (¡Ó)
VCC ¡V VSS (¡Ó)
JESD22-A114-B
Latch-Up Ta = 25¢J,
+/- Current Trigger
 +Voltage Trg  ¡VVoltage Trg EIA/JESD78
ELECTRO MIGRATION (EM) Follow JEDEC - >1.0 mA/um JESD63
Solder ability Ta = 215 ¡Ó 5¢J
Dipping depth= 1~1.5mm
Dipping 5sec MIL-STD-750C

 

Total Solutions on Failure Analysis

  • Electrical Analysis
    - Curve Tracer, Logic Analyzer,
    - Signal Generator
    - HP 4145, 4156


  • Package Level Analysis
    - X-ray, SAM
    - De-cap, Dry Plasma Etched


  • Leakage Current Analysis
    - EMMI, Liquid Crystal, Hot Spot
    - O Birch


  • Physical Analysis
    - SEM, TEM, FIB, u-scope

 

Failure Analysis

(1) X-ray Analysis

7 Golden wire / Ball Anaylysis 8

 

(2) De-Cap Analysis

1 Passivation Layer, Top side review

 

(3) Emission Analysis

2 4

 

(4) SAM

5 6

 

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