A big fabless company adopted EE Solutions multi-million-gate count design flow to tape-out a 12 million gate and 4 million gate count design with 0.15um process in a competitive short period of time. The challenges for this design are not only the huge gate count but also the timing/clock constraints.

The 0.15um library was owned by the customer, EE Solutions hence needed to tune the proprietary library in order to fit into the flow. The process involved a lot of engineering communication/conversations and as a result, it further sharpened EE Solutions' capability in dealing with different sets of library.

The hierarchical methodology was employed due to the big design. EE Solutions utilized the floor plan tool to break the chip design into several groups and take a top-level group to integrate all the groups together. However, there were still challenges for the capacity of the Place and Route tools due to the size of some groups. The complicated clock tree structure and the fast timing (350MHz) increased the difficulty of the flow.

With excellent project management skill, EE Solutions was able to monitor the progress by holding intensive meetings to share the experiences and findings among all project team members. A specific script that linked each sub-flow was established.

When the SDF was sent to the customer for timing verification, EE Solutions had the layout engineers sit in customer site to perform the physical verification job with parallel in order to expedite the tape out schedule.
The design was taped out successfully and one of them is in mass production shipment currently.