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First Pass 90nm Silicon Success
12 Million Gate Count Design
Huge Cost Reduction on PCM Chip
Low Power Design
12 Million Gate Count Design
Optical Shrink Technology
SoC/Platform Based Design
SoC/Platform Based Design

 

Success Story: Optical Shrink Technology

Chip Function
Multi-media SoC Design
 
Design Summary
  • Technology: TSMC 80nm + 1 poly 6 layer metals
  • Cell counts: 1M + 228 Macros
  • Clock speed: up to 400Mhz
  • Design Size: changed from 42mm^2 to 36mm^2
Design Challenges  
  • Voltage island (2 switched power domain, 1 stand-by domain)
  • Multi-vt
  • Clock Frequency: 370MHz
  • Hierarchical design
  • IR drop is low than 5%
  
Advantage  
  • 10% -15% Die Cost Reduction (die size reduce, yield increase)
  

EE Solutions has successfully tape-out a Multi-media SoC for a top-rated fabless company in Korea. The SoC has two embedded ARM9 processors running at 370MHz and cell count is over 1M gate plus 228 Macros. The challenge includes multiple voltage islands (2 switched power domain, 1 stand-by domain), multi-vt and the IR drop need to be less than 5%. EE Solutions implemented the Deep Submicron Design flow to successful tape-out the SoC with TSMC 80nm process with 1 poly 6 layer metals and the final die size is 6000um x 6000um.