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First Pass 90nm Silicon Success
12 Million Gate Count Design
Huge Cost Reduction on PCM Chip
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12 Million Gate Count Design
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SoC/Platform Based Design
SoC/Platform Based Design

 

Success Story: WCDMA Base Station

Chip Function
Wireless application
 
Design #1 Summary
  • Technology: UMC 0.18um 1P6M
  • Gate counts: 4M + 151 Macros (3.9M bit memory)
  • Frequency: 64MHz
  • Die size: 12.8 x 12.8mm^2
Design#2 Summary
  • Technology: 0.18um 1P6M
  • Gate counts: 3M + 206 Macros (3M bit memory)
  • Frequency: 64MHz
  • Die size: 10.6 x 10.6mm^2
Challenges
  • Floorplan methodology (handling more than 150 macros)
  • Hierarchical design planning to manage the complexity of multimillion-gate designs and achieve timing closure.
  • Fast turn around time: 6 weeks schedule from get final netlist to tape-out.
  • 5% IR drop, low IR drop implementation for high power consumption 3.5W.

A big telecom company adapted EE Solutions multi-million-gate count design flow to tape-out two 4 million gate wireless telecommunication application designs with 0.18um process within 33 days in year 2002. The designs included more than 150 hard macros and the IR drops are within 5%.

EE Solutions were a back-up alternative against a famous multi-national ASIC company. EE Solutions formed a task force for the project and closely controlled the schedule by our superior project management team. EE Solutions taped out the 2 ASICs for the customer in a short period of time and the samples were tested while the NMC company who started the project one month earlier still far away from taping out the chip.

These two ASICs are now in mass production. EE Solutions helps the customer to reduce their cost from buying ASSP instead.